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rev. 1.0 august 2006 1mx36 & 2mx18 sram - 1 - K7D321874C k7d323674c 36mb ddr sram specification 153bga with pb & pb-free (rohs compliant) * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure could result in lo ss of life or personal or ph ysical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply.
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 2 - K7D321874C k7d323674c document title 36m ddr synchronous sram revision history rev no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 1.0 remark advance preliminary preliminary final history initial document. change ac characteritics, pin capacitance, dc characteristics change samsung jedec code in id register definition correct typo draft data nov. 2005 apr. 2006 jun. 2006 aug. 2006
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 3 - K7D321874C k7d323674c ordering information organization maximum frequency part number 1mx36 400mhz k7d323674c-h(g) 1 c40 375mhz k7d323674c-h(g) 1 c37 333mhz k7d323674c-h(g) 1 c33 2mx18 400mhz K7D321874C-h(g) 1 c40 375mhz K7D321874C-h(g) 1 c37 333mhz K7D321874C-h(g) 1 c33 general description the k7d323674c and K7D321874C are 37,748,736 bit synchronous pipel ine burst mode sram devices. they are organized as 1,048,576 words by 36 bits for k7d323674c and 2,097,152 wo rds by 18 bits for K7D321874C, fabricated using samsung's advanced cmos technology. single differential hstl level clock, k and k are used to initiate the read/write operation and all internal operations are self-timed. at the rising edge of k clock, all addresses and burst control inputs are registered internally. data inputs are registered one c ycle after write addresses are asserted(late write), at the rising edge of k clock for single data rate (sdr) write operations and at risi ng and falling edge of k clock for a double data rate (ddr) write operations. data outputs are updated from output registers off the rising edge s of k clock for sdr read operations and off the rising and f alling edges of k clock for ddr read operations. free running echo cloc ks are supported which are representative of data output access time for all sdr and ddr operations. the chip is operated with 1.8~2.5v power supply and is compatible with hstl input and output. the package is 9x17(153) ball gr id array balls on a 1.27mm pitch. features ? 1mx36 or 2mx18 organizations. ? 1.8~2.5v v dd /1.5v ~1.8v ddq . ? hstl input and outputs. ? single differential hstl clock. ? synchronous pipeline mode of operation with self-timed late write. ? free running active high and ac tive low echo clock output pin. ? registered addresses, burst control and data inputs. ? registered outputs. ? double and single data rate burst read and write. ? burst count controllable with max burst length of 4 ? interleaved and linear burst mode support ? bypass operation support ? programmable impedance output drivers. ? jtag boundary scan (subset of ieee std. 1149.1) ? 153(9x17) ball grid array package(14mmx22mm) ? no output enable support. note 1. h(g) [package type] : g-pb free, h-pb
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 4 - K7D321874C k7d323674c functional block diagram k,k b 1 b 3 b 2 register ce memory array 1mx36 data out data in advance control sd/dd co clock synchronous buffer internal clock generator ce r/w ld data output strobe data output enable state machine strobe_out s/a array 2 : 1 mux data in register write buffer w/d array echo clock output 36(or 18)x2 36(or 18)x2 36(or18)x2 36(or18)x2 xdin cq,cq dq 36(or 18) select & r/w control output buffer write ce burst counter register address address comparator 2:1 mux dec. 20(or 21) 18(or 19) 18(or 19) 20(or 21) (burst write sa[0:20]( or sa[0:21]) or (2mx18) (2 stage) (2 stage) (burst address) address) pin description pin name pin description pin name pin description k, k differential clocks tck jtag test clock sa synchronous address input tms jtag test mode select sa 0 , sa 1 synchronous burst address input (sa 0 = lsb) tdi jtag test data input dq synchronous data i/o tdo jtag test data output cq, cq differential output echo clocks v ref hstl input reference voltage b 1 load external address v dd power supply b 2 burst r/w enable v ddq output power supply b 3 single/double data selection v ss gnd lbo linear burst order nc no connection zq output driver impedance control input
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 5 - K7D321874C k7d323674c package pin configurations (top view) k7d323674c(1mx36) 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq dq sa v ss b 1 v ss sa dq dq c v ss v ddq sa sa sa sa sa v ddq v ss d dq dq sa v ss (5) v dd v ss (6) sa dq dq e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq cq dq v dd v dd v dd dq cq dq g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq dq dq v dd k v dd dq dq dq j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq dq dq v ss b 2 v ss dq dq dq l v ss v ddq v ss lbo b 3 mode(7) v ss v ddq v ss m dq cq dq v dd v dd v dd dq cq dq n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq dq nc * v ss v dd (2) v ss sa dq dq r v ss v ddq v dd (4) sa sa 1 sa v dd (3) v ddq v ss t dq dq sa v ss sa 0 v ss sa dq dq u v ss v ddq tms tdi tck tdo nc v ddq v ss K7D321874C(2mx18) (1) variable address see "variable address assignment table" (2) variable address see "variable address assignment table" (3) variable address see "variable address assignment table" (4) variable address see "variable address assignment table" (5) variable address see "variable address assignment table" (6) variable address see "variable address assignment table" (7) internally nc 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b nc dq sa v ss b 1 v ss sa nc dq c v ss v ddq sa sa sa sa sa v ddq v ss d dq nc sa v ss (5) v dd v ss (6) sa dq nc e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f nc cq nc v dd v dd v dd dq nc dq g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq nc dq v dd k v dd nc dq nc j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k nc dq nc v ss b 2 v ss dq nc dq l v ss v ddq v ss lbo b 3 mode(7) v ss v ddq v ss m dq nc dq v dd v dd v dd nc cq nc n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p nc dq sa v ss v dd (2) v ss sa nc dq r v ss v ddq v dd (4) sa sa 1 sa v dd (3) v ddq v ss t dq nc sa v ss sa 0 v ss sa dq nc u v ss v ddq tms tdi tck tdo nc v ddq v ss
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 6 - K7D321874C k7d323674c variable address assignment table note : - sram density definition beyond 144mb will include the parity bits. density ball 5c (1) ball 5p (2) ball 7r (3) ball 3r (4) ball 4d (5) ball 6d (6) 32 mb sa v dd v dd v dd v ss v ss 64 mb sa sa v dd v dd v ss v ss 144 mb nc sa sa sa v ss v ss 288 mb sa sa sa sa v ss v ss 576 mb nc sa sa sa sa sa 1152 mb sa sa sa sa sa sa
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 7 - K7D321874C k7d323674c read operation(single and double) during sdr read operations, addresses and controls are registered at the first rising edge of k clock and then the internal arr ay is read between first and second rising edges of k clock. data outputs are updated from output registers off the second rising edg e of k clock. during ddr read operations, addresses and controls are registered at the first rising edge of k clock, and then the in ternal array is read twice between first and second rising edges of k cl ock. data outputs are updated from output registers sequentia lly by burst order off the second rising and falling edge of k clock. interleave and linear burst opera tion is controlled by lbo pin and the burst count is controllable with the maximum burst length of 4. to avoid data contention,at least two nop operations are required between the last read and the first write operation. write operation(late write) during sdr write operations, addresses and cont rols are registered at the first rising edge of k clock and data inputs are regi stered at the following rising edge of k clock. during ddr write operati ons, addresses and controls are registered at the first rising edge of k clock and data inputs are registered twic e at the following rising and falling edge of k clock. write addresses and data inpu ts are stored in the data in registers until the next write operation, and only at the next write operation are data inputs fully writ ten into sram array. echo clock operation free running type of echo clocks are generated from k clock regardless of read, write and nop operations. they will stop operat ion only when k clock is in the stop mode. echo clocks are designed to repres ent data output access time and this allows t he echo clocks to be used as reference to captur e data outputs. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in registers instead of sram array. programmable impedance output driver this hstl late write sram has been designed with progra mmable impedance output buffers. the srams output buffer imped- ance can be adjusted to match the system data bus impedance, by connecti ng a external resistor (rq) between the zq pin of the sram and v ss . the value of rq must be five times the value of the intended line impedance driven by the sram. for example, a 250 ? resistor will give an output buffer impedance of 50 ? . the allowable range of rq is from 175 ? to 350 ? . internal circuits evaluate and periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. one evaluation occurs every 32 clock cycles, with each evaluat ion moving the output buffer impedance level only one step at a time toward the optimum level. impedance updates occur when the sram is in high-z state, and thus ar e triggered by write and deselec t operations. updates will also be triggered wi th g high initiated high-z state, providing the specified g setup and hold times a re met. impedance match is not instantaneous upon power-up. in order to guarantee optimum output driver impedance, the sram requires a minimum number of non-read cycles (1,024) after power-up. th e output buffers can also be programmed in a minimum impedance configuration by connecting zq to v ss or v ddq . power-up/power-down supply voltage sequencing the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simult aneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down.
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 8 - K7D321874C k7d323674c truth table note : - b(both) is din in write cycle and dout in read cycle. byte write function is not suppo rted. x means "don't care". - k & k are complementary. k b1 b2 b3 dq operation h l x hi-z no operation, pipeline high-z l h h dout load address, single read lhl dout load address, double read l l h din load address, single write l l l din load address, double write h h x b increment address, continue 4 burst operation for interleaved burst (lbo = v ddq ) note : - for interleave burst lbo = v ddq is recommended. if lbo = v dd , it must not exceed 2.63v. interleaved burst mode case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 burst sequence table 4 burst operation fo r linear burst (lbo = v ss ) linear burst mode case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 output tristate truth table k operation dq (n) dq (n+1) write (b2=l) x high-z deselect (nop) (b1=h, b2=l) x high-z
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 9 - K7D321874C k7d323674c note : 1. state transitions ; b 1 =(load address), b 1 =(increment address, continue) b 2 =(read), b 2 =(write) b 3 =(single data rate), b 3 =(double data rate) bus cycle state diagram load new address increment address increment address increment address increment address read sdr write sdr read ddr write ddr b 2 , b 3 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 no op power up b 2 , b 3 b 1 b 2 , b 3 b 1 b 2 , b 3 b 1 b 1 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 10 K7D321874C k7d323674c recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v ddq +0.3, v ih (max)ac= 2.6 v (2.1v for dqs) (pulse width 20% of cycle time). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.0v (-0.5v for dqs) (pulse width 20% of cycle time). parameter symbol min typ max unit note core power supply voltage v dd 1.7 2.5 2.6 v output power supply voltage v ddq 1.4 1.5 1.9 v input high level voltage v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low level voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 1.0 v absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use envi ronment. see enclosed thermal impeda nce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.13 v output supply voltage relative to v ss v ddq -0.5 to 2.3 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.3v max )v output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c maximum junction temperature t j 110 c maximum power dissipation p d 3.0 w dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 ? rq 300 ? . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 ? rq 300 ? . parameter symbol min max unit note average power supply operating current(x36) (cycle time = t khkh min) i dd40 i dd37 i dd33 - 700 650 600 ma 1,2 average power supply operating current(x18) (cycle time = t khkh min) i dd40 i dd37 i dd33 - 650 600 550 ma 1,2 stop clock standby current (v in =v dd -0.2v or 0.2v fixed, k=low, k =high) i sb1 - 300 ma 1 input leakage current (v in =v ss or v ddq ) i li -3 3 a output leakage current (v out =v ss or v ddq ) i lo -5 5 a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v3 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 11 K7D321874C k7d323674c pin capacitance note : periodically sampled and not 100% tested.(t a =25 c, f=500mhz) parameter symbol test condition typ max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf ac test conditions (t a =0 to 70 c, v dd =2.37 -2.63v, v ddq =1.5v) parameter symbol value unit note input high/low level v ih /v il 1.25/0.25 v - input reference level v ref 0.75 v - input rise/fall time t r /t f 0.5/0.5 ns - output timing reference level 0.75 v - clock input timing reference level cross point v - output load see below - ac input characteristics parameter symbol min max unit note ac input logic high v ih (ac) v ref + 0.4 v - ac input logic low v il (ac) v ref - 0.4 v - clock input differential voltage v dif (ac) 0.8 v - v ref peak-to-peak ac voltage v ref (ac) 5% v ref (dc) v - ck ck v ih (ac) v ref v il (ac) ac input definition setup time hold time v dif (ac)
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 12 K7D321874C k7d323674c ac timing characteristics notes : 1. the maximum cycle time must be limited to guarantee ac timing specification. 2. this parameter is guaranteed by design, and may not be tested at values shown in the table. 3. this parameter refers to cq and cq rising and falling edges. 4. k and k clocks must be used differentially to meet ac timing specifications. parameter symbol -40 -37 -33 units notes min max min max min max clock clock cycle time t khkh 2.50 2.67 3.00 ns 1 clock high pulse width t khkl 1.15 1.25 1.40 ns clock low pulse width t klkh 1.15 1.25 1.40 ns setup times address setup time t avkh 0.30 0.33 0.35 ns control(b1,b2,b3) setup time t bvkh 0.30 0.33 0.35 ns data setup time t dvkx 0.20 0.25 0.30 ns 2 hold times address hold time t khax 0.30 0.33 0.35 ns control(b1,b2,b3) hold time t khbx 0.30 0.33 0.35 ns data hold time t kxdx 0.20 0.25 0.30 ns 2 output times echo clock high pulse width t chcl t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 ns 2 echo clock low pulse width t clch t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 ns 2 clock crossing to echo clock t kxch 1.0 2.5 1.0 2.5 1.0 2.5 ns 3 clock crossing to echo clock t kxcl 1.0 2.5 1.0 2.5 1.0 2.5 ns 3 echo clock high to output valid t khqv 0.20 0.20 0.20 ns echo clock low to output valid t clqv 0.20 0.20 0.20 ns echo clock high to output hold t chqx -0.20 -0.20 -0.20 ns echo clock low to output hold t clqx -0.20 -0.20 -0.20 ns echo clock high to output high-z t chqz 0.20 0.20 0.20 ns echo clock high to output low-z t chlz -0.20 -0.20 -0.20 ns 50 ? 50 ? ac test output load 25 ? 5pf dq 0.75v 5pf 0.75v 50 ? 50 ? 0.75v
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 13 K7D321874C k7d323674c nop continue k k b1 sa t avkh t khax cq nop 12 3 4 5 6 7 81012 11 b2 b3 cq dq read (burst of 4) read (burst of 2) read (burst of 4) nop write continue write (burst of 4) read 9 continue read read (burst of 4) continue read a 0 a 1 a 2 a 3 q x2 q 01 q 02 q 03 q 04 q 51 q 52 q 53 q 54 q 11 q 12 d 21 d 23 d 24 d 22 q 31 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t dvkh t khdx t khkh undefined don?t care a 5 note 1. q 01 refers to output from address a. q 02 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) one clock cycle after no p detected or after no pending data requests are present. 3. doing more than one read continue or write continue will cause the address to wrap around. timing waveforms for do uble data rate cycles (burst length=4, 2) t clqv t clqx t kxcl t chcl t clch
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 14 K7D321874C k7d323674c timing waveforms for si ngle data rate cycles note : 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after no p detected or after no pending data requests are present. 3. this devices supports cycle l engths of 1, 2, 4. continue(b1=high, b2=high, b3=x) up to three times following a b1 operation. any further continue assertions constitute invalid operations. 4. this device will have an address wraparound if further continues are applied. nop continue t khkh t avkh t khax nop 1 2 3 4 5 6 7 8 10 12 11 read (burst of 2) read read (burst of 4) nop write continue write (burst of 2) read 9 continue read continue read continue read a 0 a 1 a 2 a 3 q x1 d 22 d 21 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t dvkh t khdx t klkh q 31 q 01 q 02 q 03 q 04 q 11 undefined don?t care t khkl k k b1 sa b2 b3 dq cq cq (burst length=4, 2, 1) (burst of 1) t chcl t clch t kxcl
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 15 K7D321874C k7d323674c ieee 1149.1 test access po rt and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo sa sa tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag fu nctions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in confor m- ance with ieee 1149.1, the sram contains a tap controller, instru ction register, bypass register and id register. the tap contr ol- ler has a standard 16-state machine that resets internally upon pow er-up, therefore, trst signal is not required. it is possibl e to use this device without utilizing the tap. to disable the tap contro ller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. input terminators are switched off. 2. tdi is sampled as an input to the fi rst id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. 5. private1 and private2 are rese rved for the exclusive use of sam- sung. this instruction should not be used. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 private3 bypass register 3,5 1 0 0 sample boundary scan register 4 1 0 1 private2 bypass register 3,5 1 1 0 private1 bypass register 3,5 1 1 1 bypass bypass register 3
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 16 K7D321874C k7d323674c boundary scan exit order(x36) * reserved for mode pin 1 5p v dd (2) 38 5c sa 25rsa 1 39 4a sa 35tsa 0 40 4c sa 46rsa 41 4d v ss (2 57tsa 42 3a sa 67rv dd (2) 43 3b sa 77psa 44 3c sa 88tdq1 45 3d sa 99tdq2 46 2b dq19 10 8p dq10 47 1b dq20 11 7m dq0 48 2d dq28 12 9p dq12 49 3f dq18 13 8m cq (3) 50 1d dq30 14 9m dq3 51 2f cq(3) 15 7k dq9 52 1f dq21 16 8k dq11 53 3h dq27 17 9k dq13 54 2h dq29 18 6l mode 55 1h dq31 19 5h k 56 5a zq(1) 20 5g k 57 5b b 1 21 9h dq4 58 5k b 2 22 8h dq6 59 5l b 3 23 7h dq8 60 4l lbo 24 9f dq14 61 1k dq22 25 8f cq(3) 62 2k dq24 26 9d dq5 63 3k dq26 27 7f dq17 64 1m dq32 28 8d dq7 65 2m cq (3) 29 9b dq15 66 1p dq23 30 8b dq16 67 3m dq35 31 7d sa 68 2p dq25 32 7c sa 69 1t dq33 33 7b sa 70 2t dq34 34 7a sa 71 3r v dd (2) 35 6d v ss (2) 72 3t sa 36 6c sa 73 4r sa 37 6a sa 74 7u nc boundary scan exit order(x18) * reserved for mode pin 15pv dd (2) 28 5c sa 25rsa 1 29 4a sa 35tsa 0 30 4c sa 46rsa 31 4d v ss (2) 57tsa 32 3a sa 67rv dd (2) 33 3b sa 77psa 34 3c sa 88tdq1 35 3d sa 36 2b dq10 99pdq2 10 8m cq (3) 37 1d dq11 38 2f cq(3) 11 7k dq0 39 3h dq9 12 9k dq3 13 6l mode 40 1h dq12 14 5h k 41 5a zq(1) 15 5g k 42 5b b1 43 5k b2 16 8h dq6 44 5l b3 45 4l lbo 17 9f dq4 46 2k dq15 18 7f dq8 47 1m dq13 19 8d dq7 20 9b dq5 48 3m dq17 21 7d sa 49 2p dq16 22 7c sa 50 1t dq14 23 7b sa 51 3p sa 24 7a sa 52 3r v dd (2) 25 6d v ss (2) 53 3t sa 26 6c sa 54 4r sa 27 6a sa 55 7u nc note : 1. this pin is place holder for higher density. tdo will be low for v ss and high for v dd scan register definition part instruction register bypass register id register boundary scan 1m x 36 3 bits 1 bits 32 bits 74 bits 2m x 18 3 bits 1 bits 32 bits 55 bits
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 17 K7D321874C k7d323674c jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 1.7 2.5 2.6 v input high level v ih 0.65*v dd -v dd +0.3 v input low level v il -0.3 - 0.35*v dd v output high voltage(i oh =-2ma) v oh 0.75*v dd -v dd v output low voltage(i ol =2ma) v ol v ss - 0.25*v dd v jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 5. parameter symbol min unit note input high/low level v ih /v il v dd /0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level v dd /2 v 1 jtag timing diagram tck tms tdi tdo t chch t chcl t clch t mvch t chmx t dvch t chdx t clqv id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit (0) 1m x 36 0000 01000 00100 xxxxxx 00011001110 1 2m x 18 0000 01001 00011 xxxxxx 00011001110 1
rev. 1.0 august 2006 1mx36 & 2mx18 sram - 18 K7D321874C k7d323674c 153 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja 19.5 c/w junction to case theta_jc 0.9 c/w junction to board theta_jb 6.9 c/w note : 1. all dimensions are in millimeters. 2. solder ball to pcs offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. 153 bga package dimensions 1.27 7654321 0.050 b c d e f g h j k l m n p r t ua 1.27 0.050 ? bottom view 0.3/0.012max 153- ? 0.030 0.006 14.00 0.10 0.551 0.004 22.00 0.10 0.866 0.004 12.50 0.10 0.492 0.004 0.60 0.10 0.024 0.004 20.50 0.10 0.807 0.004 0.56 0.04 0.022 0.002 0.90 0.10 0.035 0.004 2.21 0.087 top view 0.006 0.15 max 0.75 0.15 max 98

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